Total loop impedance Zs measurement
Inspection Testing · Lesson 17 · Advanced
Purpose
Measure or derive total loop impedance Zs while understanding parallel paths, no-trip methods and instrument effects.
Learning objectives
- Select a safe valid method
- Protect connected equipment
- Interpret measured versus design values
- Diagnose without bypassing protective evidence
Zs is the complete earth-fault loop at a circuit point. A live loop tester injects a signal and observes voltage response; connected bonding and parallel paths can make the measured value lower than the designed CPC path.
Core theory
Complete continuity/polarity/IR evidence, restore protective conductors, identify RCDs and sensitive loads, then use an appropriate high-current or no-trip method under controlled live conditions.
Record the worst relevant point and circuit state. No-trip algorithms can have greater uncertainty and may be affected by supply noise, RCD type or electronics; follow instrument data.
Compare measured Zs with calculated Ze+(R1+R2) and investigate large differences. A low result from parallel pipe/data paths does not prove the circuit CPC is intact.
| Term | Meaning | Symbol | Unit |
|---|---|---|---|
| Zs | Total earth-fault loop impedance at a point | Not applicable | Not applicable |
| No-trip test | Low-current/controlled loop method intended to avoid RCD operation | Not applicable | Not applicable |
| Parallel earth path | Additional conductive route lowering measured loop impedance | Not applicable | Not applicable |
Assumptions: Supplied values and device limits are fictional design evidence; Instrument uncertainty and current edition data remain to be checked.
- Difference: Measured value is much lower than calculated designed path.
- Hypothesis: Parallel bonding/metalwork or method effects may dominate.
- Decision: Do not discard CPC evidence; reconcile paths, instrument and circuit data.
The low live reading is not automatic proof of a superior CPC; investigate the discrepancy.
Reasonableness check: The conclusion retains units, test boundary and protective-device context; one favorable reading cannot excuse an unsafe method.
- Testing connected electronics at an unsuitable DC voltage
- Treating parallel paths as the designed CPC
- Comparing a measured Zs with the wrong device curve or an unqualified tabulated value
Where this appears in practice
IR and loop verification provide complementary evidence: insulation limits unintended current paths while loop impedance supports automatic disconnection under faults.
Knowledge check
Can a low live Zs replace a failed CPC continuity test?
No. Parallel paths can mask the missing designed protective conductor.
Answer: No. Parallel paths can mask the missing designed protective conductor.
Practical exercise
Compare calculated and measured Zs sets and identify parallel paths, wrong circuit identity and unstable supply cases.
Summary
- Choose voltage and connections from actual equipment
- Loop boundaries must be explicit
- Compare results with exact current design evidence
Sources and review
- BS 7671 and Guidance Note 3: Inspection & Testing: IET; BS 7671:2018+A4:2026 / GN3 10th edition; transition rules apply; United Kingdom
- Guidance Note 3 errata and diverted-neutral safety note: IET; GN3 9th-edition errata; use current GN3 procedure; United Kingdom
- GS38: Electrical test equipment for low-voltage systems: HSE; Fourth edition; Great Britain
Editorial review date: 2026-08-22. Professional electrical review is pending.