Testing Zs with loop testers
Protection Fault Analysis · Lesson 26 · Advanced
Purpose
Plan and interpret earth-fault loop impedance verification while minimizing unnecessary live testing.
Learning objectives
- Choose dead or live evidence
- Select an appropriate loop mode
- Account for parallel paths
- Record and reconcile results
A loop tester estimates impedance by applying a controlled test stimulus and observing voltage response. Because conventional loop testing is live, verification should obtain adequate evidence with the least exposure reasonably practicable.
Core theory
Zs can be supported by verified Ze information plus dead-test R1+R2, by calculation, or by a justified live loop test. The selected method must fit the circuit, protective device, RCD, connected equipment, and current guidance.
No-trip modes use a smaller or shaped stimulus to reduce RCD operation but may have lower resolution or greater susceptibility to supply noise. Parallel protective paths can reduce a live measured value without proving the intended CPC path alone.
Before a permitted live test, establish polarity, earthing, instrument CAT/voltage/range, leads, expected value, barriers, PPE, and emergency controls. Reconcile the result with design values, temperature, uncertainty, and device limits.
| Term | Meaning | Symbol | Unit |
|---|---|---|---|
| Loop tester | Instrument estimating loop impedance from a controlled live test | Not applicable | Not applicable |
| No-trip test | Low-disturbance loop method intended to avoid operating an RCD | Not applicable | Not applicable |
| Parallel path | Additional conductive return path that can lower measured impedance | Not applicable | Not applicable |
Assumptions: Values describe the same supply state and circuit path.
- Components: Identify external and circuit portions.
- Add: Zs = 0.24 Ω + 0.61 Ω = 0.85 Ω.
- Verify: Apply the required design/test basis and compare with the exact device criterion.
The initial combined value is 0.85 Ω.
Reasonableness check: Total loop impedance cannot be less than either positive series component in this simplified model.
- Live testing by habit
- Assuming a no-trip mode is exact
- Treating a low result as proof of CPC continuity
Where this appears in practice
Zs evidence supports automatic-disconnection verification and diagnosis of unexpected loop-path resistance.
Knowledge check
Why can a live Zs result be lower than Ze plus dead-test R1+R2?
Parallel conductive paths may be included. Investigate and document the evidence rather than forcing the values to match.
Answer: Parallel conductive paths may be included. Investigate and document the evidence rather than forcing the values to match.
Practical exercise
Write a decision tree choosing enquiry, calculation, dead testing, or justified live testing for three fictional circuits.
Summary
- Minimise live testing
- Understand test-mode limitations
- Reconcile all evidence
Sources and review
- Guidance Note 6: Protection Against Overcurrent: IET; 10th edition, BS 7671:2018+A4:2026; United Kingdom
- Inspection and Testing FAQs: IET; Current online guidance; United Kingdom
- Electricity at Work Regulations 1989: HSR25: Health and Safety Executive; Third edition; Great Britain
Editorial review date: 2026-08-21. Professional electrical review is pending.