Timers and counters in ladder logic
Industrial Control · Lesson 24 · Advanced
Purpose
Apply timers and counters with explicit time base, edge behavior, retention, reset and overflow semantics.
Learning objectives
- Trace data and energy paths
- Predict deterministic state changes
- Design maintainable panel implementation
- Verify before handover
IEC-style timer/counter concepts are portable, but exact invocation, data types, retentivity and task behavior must be confirmed for the target runtime.
Core theory
TON delays the true output while input remains true; TOF delays clearing; pulse timers create a timed pulse. State elapsed-time and reset behavior.
Counters normally count qualifying edges, not every scan that an input remains true. Define rising/falling edge, preset, reset priority, retained value and overflow response.
Time accuracy includes task scheduling and I/O delay. Do not use a basic software timer alone where a safety response time or independent protective function is required.
| Term | Meaning | Symbol | Unit |
|---|---|---|---|
| TON | On-delay timer function block | Not applicable | Not applicable |
| Rising edge | Transition from false to true | Not applicable | Not applicable |
| Retentive | State intentionally preserved across defined conditions | Not applicable | Not applicable |
Observed response ≤ input delay + task interval/jitter + output delayA timing budget boundary, not a universal equality.
timeAssumptions: The supplied PLC behavior and equipment data are authoritative for the example; Safety functions are separately specified and validated.
- Edge: There is one rising edge.
- Count: A correctly edge-triggered counter increments once, not 50 times.
- Reset: Confirm reset priority and retained behavior in the exact runtime.
The count increases by one for the single qualifying edge.
Reasonableness check: The result follows the declared scan, wiring and assembly boundaries rather than assuming every platform behaves identically.
- Treating field input state and program contact instruction as the same thing
- Writing one output from several uncontrolled locations
- Using spare physical space as proof of thermal or EMC capacity
Where this appears in practice
PLC and panel engineering connects field signals, deterministic software, power/control distribution, safety functions, documentation and commissioning evidence.
Knowledge check
Should a counter increment on every scan while its input stays true?
No. Edge-counting logic records the defined transition once.
Answer: No. Edge-counting logic records the defined transition once.
Practical exercise
Simulate timer/counter behavior through bounce, power cycle, simultaneous reset and counter maximum.
Summary
- PLC logic operates on a sampled process image
- Panel layout is an electrical/thermal/EMC design
- Commissioning must prove hardware, software and safety behavior
Sources and review
- IEC 61131-3:2025: Programmable-controller languages: IEC; 2025; International
- IEC 60204-1:2016+AMD1:2021: Electrical equipment of machines: IEC; 6.1; International
- IEC 61439-1:2020: Low-voltage assemblies: general rules: IEC; 2020 with current corrigenda; International
Editorial review date: 2026-08-22. Professional electrical review is pending.